The present invention relates to a method of testing semiconductor integrated circuits whereby a plurality of semiconductor integrated circuit elements (semiconductor chips) are tested simultaneously for electric characteristics and to a testing board for use in the testing method.
In the process of fabricating a conventional semiconductor integrated circuit device, an electrical connection is provided between a semiconductor chip and a leadframe by a bonding wire and then the semiconductor chip and the leads of the leadframe are sealed with a resin or ceramic to be mounted on a printed circuit board.
To meet the demand for an electronic device reduced in both size and price, there has been developed a method of mounting, on a circuit board, a semiconductor integrated circuit device as a bare chip cut out of a semiconductor wafer. The bare chip used in the method is preferably a quality-assured bare chip supplied at lower price. For the quality assurance of a bare chip, it is preferable, in terms of cost reduction, to perform a simultaneous burn-in process with respect to a plurality of semiconductor chips formed in a single semiconductor wafer.
In accordance with a known testing method, a simultaneous burn-in process is performed with respect to a plurality of semiconductor chips formed in a semiconductor wafer by using a contactor having probe terminals to be connected to the respective testing electrodes of the semiconductor chips. In this case, it is required to apply power-source voltage or ground voltage to the testing electrode of each of the semiconductor chips. For individual application of the power-source voltage or ground voltage to the testing electrodes of the semiconductor chips, however, a large number of wires should be routed over the contactor or semiconductor wafer, which is not realistic.
To overcome the drawback of the method, there has been proposed another method wherein a common power-source-voltage supply line or ground-voltage supply line (hereinafter generally referred to as common voltage supply lines) is provided such that power-source voltage or ground voltage is applied to each of the testing electrodes therethrough, thus avoiding the necessity for routing a large number of wires.
However, the provision of such common voltage supply lines on the contactor or semiconductor wafer is disadvantageous in that, if a defective semiconductor chip electrically short-circuited exists in the semiconductor wafer, the common power-source-voltage supply line and the common ground-voltage supply line are short-circuited via the defective semiconductor chip.
To eliminate the disadvantage, U.S. patent application Ser. No. 08/358609 (Japanese Unexamined Patent Publication No. 7-169806) has proposed a method of testing semiconductor integrated circuits wherein the individual semiconductor chips are preliminarily tested for electric characteristics before a burn-in process is performed thereto and the semiconductor chip judged to be defective in the preliminary test is coated with a liquid insulating agent. The liquid insulating agent is then cured to form a non-conductive layer over the testing electrode of the defective semiconductor chip, thereby preventing a current flow through the defective semiconductor chip. After that, a simultaneous burn-in process is performed with respect to the other conforming semiconductor chips.
Although the conventional method of testing semiconductor integrated circuits can screen out the semiconductor chip judged to be defective in the preliminary electric characteristic test before the burn-in process, it is still disadvantageous in that, if a defective semiconductor chip is produced for some reason during the burn-in process, the burn-in process cannot be performed with respect to the other conforming semiconductor chips.
For example, there are cases where some disturbance causes a latch-up phenomenon in a CMOS integrated circuit during the burn-in process so that an abnormal current flows through the CMOS integrated circuit having undergone the latch-up phenomenon. Since a large current flows between the common power-source voltage line and the common ground voltage line via the semiconductor chip having undergone the latch-up phenomenon, the burn-in process cannot be performed with respect to the other semiconductor chips.
Moreover, since wiring is more complicated and the density of a current flowing through the wiring is higher in a semiconductor integrated circuit becoming denser and increasingly miniaturized, the current density excessively increased by some disturbance in the burn-in process may cause an electromigration, which leads to a short circuit in the wiring. In this case also, a large current flows between the common power-source voltage line and the common ground voltage line via the semiconductor chip having undergone the electromigration and the burn-in process cannot also be performed with respect to the other semiconductor chips.
If a defective semiconductor chip is produced during the burn-in process for some reason and an extraordinarily large quantity of current flows through the defective semiconductor chip, the temperature of the defective semiconductor chip is increased to a high degree so that another conforming semiconductor chip adjacent to the defective semiconductor chip is also heated to a high temperature, resulting in abnormal operation. Thus, even when the defective semiconductor chip and the conforming semiconductor chip are not connected to the common voltage supply line, the burn-in process cannot be performed with respect to the conforming semiconductor chip as long as they are formed in a single wafer.
To circumvent the occurrence of a reversible short circuit such as the latch-up phenomenon and an irreversible short circuit in one semiconductor chip, which prevents the application of a voltage from the common voltage supply line to another semiconductor chip or the testing of the electric characteristics of a conforming semiconductor chip formed adjacent to a defective semiconductor chip abnormally heated on a single semiconductor wafer, a fuse may be interposed between the voltage supply line and the testing electrode of the semiconductor chip, thereby electrically disconnecting the defective semiconductor chip from the voltage supply line.
However, the fuse interposed between the voltage supply line and the testing electrode presents the problems that, once a defective semiconductor chip is produced, the fuse melts and needs replacing and that, once an irreversible short circuit such as the latch-up phenomenon occurs, the electric characteristics cannot be tested even when the irreversible short circuit is eliminated.
In view of the foregoing, it is therefore a first object of the present invention to ensure the testing of the electric characteristics of a plurality of semiconductor chips with the application of a voltage to the respective testing electrodes of the semiconductor chips without using a fuse. A second object of the present invention is to ensure the testing of the electric characteristics of a plurality of a semiconductor chips with the application of a voltage supplied from a common voltage supply line to the respective testing electrodes of the semiconductor chips without using a fuse.
A method of testing semiconductor integrated circuits according to the present invention comprises the step of simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to respective testing electrodes of the semiconductor integrated circuit elements, the step including the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via at least one PTC (Positive Temperature Coefficient) element.
In the method of testing semiconductor integrated circuits according to the present invention, the voltage is applied to each of the testing electrodes of the semiconductor integrated circuit elements via the corresponding PTC element. Therefore, if one of the semiconductor chips is defective in the first place or a defective semiconductor chip is produced in the step and a large quantity of current flows through the defective semiconductor chip, the large quantity of current also flows through the PTC element connected to the defective semiconductor chip so that the temperature of the PTC element is increased to a high degree, which remarkably increases the resistance thereof. As a result, the voltage is no more applied to the defective semiconductor chip and the semiconductor chips other than the defective one are no more heated to a high temperature, which allows excellent testing of the other semiconductor chips.
Once the cause of the defective semiconductor chip through which the large quantity of current has flown is eliminated, the semiconductor chip returns to a normal temperature so that the temperature of the PTC element connected to the semiconductor chip is also lowered and the voltage is applied again to the semiconductor chips.
In the method of testing semiconductor integrated circuits according to the present invention, the step preferably includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via the plurality of PTC elements provided in a one-to-one relationship for the semiconductor integrated circuit elements.
In the arrangement, even when an extraordinarily large quantity of current flows through the defective semiconductor chip, the semiconductor chip adjacent to the defective one is not heated to a high temperature, which allows excellent testing of the semiconductor chips other than the defective one.
In the method of testing semiconductor integrated circuits according to the present invention, the step preferably includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via the plurality of PTC elements provided in a one-to-one relationship for individual blocks formed by dividing the semiconductor integrated circuit elements into groups.
In the arrangement, even when an extraordinarily large quantity of current flows through the defective semiconductor chip, the semiconductor chips contained in the blocks other than the block containing the defective semiconductor chip are not heated to a high temperature, which allows excellent testing of the semiconductor chips contained in the other blocks.
In the method of testing the semiconductor integrated circuits, the step preferably includes the step of applying the voltage from a common voltage supply line to the respective testing electrodes of the semiconductor integrated circuit elements.
This prevents the application of the voltage to the defective semiconductor integrated circuit element and the occurrence of a short circuit in the power-source voltage line and ground line via the defective semiconductor chip, resulting in normal application of the voltage to the other semiconductor chips. Consequently, the other semiconductor chips can excellently be tested irrespective of the application of the voltage from the common voltage supply line to the respective testing electrodes of the semiconductor integrated circuit elements.
In the method of testing semiconductor integrated circuits according to the present invention, the step preferably includes a burn-in process.
Even when an extraordinarily large quantity of current flows through the defective semiconductor chip in the burn-in process, the arrangement allows a burn-in process to be excellently performed with respect to the other semiconductor chips.
In the method of testing semiconductor integrated circuits according to the present invention, the plurality of semiconductor integrated circuit elements are preferably formed in a semiconductor wafer and the step preferably includes the step of performing a wafer-level burn-in process with respect to the semiconductor integrated circuit elements formed in the wafer.
Even when an extraordinarily large quantity of current flows through the defective semiconductor chip formed in the semiconductor wafer during the burn-in process, the arrangement allows a burn-in process to be performed excellently with respect to the other semiconductor chips formed in the same semiconductor wafer.
In the method of testing semiconductor integrated circuits according to the present invention, the plurality of semiconductor integrated circuit elements are preferably mounted on a burn-in board and the step preferably includes the step of performing a simultaneous burn-in process with respect to the semiconductor integrated circuit elements.
Even when an extraordinarily large quantity of current flows through the defective semiconductor chip mounted on the burn-in board during the burn-in process, the arrangement allows a burn-in process to be performed excellently with respect to the other semiconductor chips mounted on the same semiconductor wafer.
In the method of testing semiconductor integrated circuits according to the present invention, the PTC element is preferably a polymer PTC element.
Since the polymer PTC element has low resistance in the steady state, it is less likely to exert adverse effects on the testing of the electric characteristics. On the other hand, the polymer PTC element has extremely high resistance in a high-temperature state so that the application of the voltage to the defective semiconductor chip is surely prevented.
A testing board according to the present invention is for simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to respective testing electrodes of the semiconductor integrated circuit elements and comprises: a plurality of connection terminals provided on a substrate to be connected to the respective testing electrodes of the semiconductor integrated circuit elements; a voltage supply line provided in the substrate to supply the voltage to the connection terminals; and at least one PTC element provided on the substrate to be interposed between the voltage supply line and at least one of the connection terminals.
Since the PTC element is connected between the voltage supply line and at least one of the connection terminals in the testing board according to the present invention, the voltage is supplied to each of the testing electrodes of the semiconductor integrated circuit elements via the corresponding PTC element. Consequently, if one of the semiconductor chips is defective in the first place or a defective semiconductor chip is produced in the step and an extraordinarily large quantity of current flows through the defective semiconductor chip, the large quantity of current also flows through the PTC element connected to the defective semiconductor chip so that the temperature of the PTC element is increased to a high degree, which remarkably increases the resistance thereof. As a result, the voltage is no more applied to the defective semiconductor chip and the semiconductor chips other than the defective one are no more heated to a high temperature, which allows excellent testing of the other semiconductor chips.
Once the cause of the defective semiconductor chip through which the large quantity of current has flown is eliminated, the semiconductor chip returns to a normal temperature so that the temperature of the PTC element connected to the semiconductor chip is also lowered and the voltage is applied again to the semiconductor chip.
In the testing board according to the present invention, the testing board is preferably a probe card for simultaneously testing the electric characteristics of the semiconductor integrated circuit elements formed in a semiconductor wafer and the connection terminals are preferably probe terminals positioned on the substrate to correspond to the respective testing electrodes of the semiconductor integrated circuit elements.
Even when an extraordinarily large quantity of current flows through the defective semiconductor chip formed in the semiconductor wafer, the arrangement allows an excellent burn-in process to be performed with respect to the other semiconductor chips formed in the same semiconductor wafer.
In the case where the testing board according to the present invention is a probe card, the probe terminals are preferably provided on one side of the substrate, the voltage supply line is preferably provided on the other side of the substrate, and the plurality of PTC elements are preferably provided on the other side of the substrate to correspond to the probe terminals in a one-to-one relationship.
By thus providing the probe terminals on one side of the substrate and the voltage supply line as well as the PTC elements on the other side of the substrate, a sufficiently large region is allowed for the PTC elements so that the PTC elements are easily provided for the probe terminals in a one-to-one relationship.
In the case where the testing board according to the present invention is a probe card, the voltage supply line is preferably a common voltage supply line connected in common to the plurality of probe terminals.
The arrangement reduces the number of voltage supply lines and facilitates the placement of the voltage supply lines.
In the case where the testing board according to the present invention is a probe card and the voltage supply line is a common voltage supply line, the probe terminals and the voltage supply line are preferably provided on one side of the substrate and the plurality of PTC elements are preferably provided on peripheral portions of one side of the substrate to correspond to individual blocks formed by dividing the probe terminals into groups in a one-to-one relationship.
This eliminates the necessity to provide contacts for connecting the plurality of probe terminals to the common voltage supply line through the card body, so that the manufacturing of the probe card is facilitated.
In the testing board according to the present invention, the PTC element is preferably characterized in that the resistance thereof is increased significantly from a value in a steady state when the temperature of the PTC element substantially exceeds 100xc2x0 C.
The arrangement allows the testing board to be used in a burn-in process performed at a temperature lower than 100xc2x0 C., e.g., on the order of 80xc2x0 C.
In the testing board according to the present invention, the PTC element is preferably a polymer PTC element.
Since the polymer PTC element has low resistance in the steady state, it is less likely to exert adverse effects on the testing of the electric characteristics. On the other hand, the polymer PTC element has extremely high resistance in a high-temperature state so that the application of the voltage to the defective semiconductor chip is surely prevented.